sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 1 post office box 655303 ? dallas, texas 75265 members of the texas instruments widebus ? family output ports have equivalent 25- w series resistors, so no external resistors are required state-of-the-art epic- ii b ? bicmos design significantly reduces power dissipation latch-up performance exceeds 500 ma per jedec standard jesd-17 typical v olp (output ground bounce) < 0.8 v at v cc = 5 v, t a = 25 c high-impedance state during power up and power down distributed v cc and gnd pin configuration minimizes high-speed switching noise flow-through architecture optimizes pcb layout package options include plastic 300-mil shrink small-outline (dl), thin shrink small-outline (dgg) packages and 380-mil fine-pitch ceramic flat (wd) package using 25-mil center-to-center spacings description these 20-bit transparent d-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. they are particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. the 'abt162841 can be used as two 10-bit latches or one 20-bit latch. while the latch-enable (1le or 2le) input is high, the q outputs of the corresponding 10-bit latch follow the data (d) inputs. when le is taken low, the q outputs are latched at the levels set up at the d inputs. a buffered output-enable (1oe or 2oe ) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the outputs, which are designed to sink up to 12 ma, include equivalent 25- w series resistors to reduce overshoot and undershoot. oe does not affect the internal operation of the latches. old data can be retained or new data can be entered while the outputs are in the high-impedance state. copyright ? 1997, texas instruments incorporated unless otherwise noted this document contains production data information current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus and epic- ii b are trademarks of texas instruments incorporated. sn54abt162841 . . . wd package sn74abt162841 . . . dgg or dl package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1oe 1q1 1q2 gnd 1q3 1q4 v cc 1q5 1q6 1q7 gnd 1q8 1q9 1q10 2q1 2q2 2q3 gnd 2q4 2q5 2q6 v cc 2q7 2q8 gnd 2q9 2q10 2oe 1le 1d1 1d2 gnd 1d3 1d4 v cc 1d5 1d6 1d7 gnd 1d8 1d9 1d10 2d1 2d2 2d3 gnd 2d4 2d5 2d6 v cc 2d7 2d8 gnd 2d9 2d10 2le
sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 2 post office box 655303 ? dallas, texas 75265 description (continued) when v cc is between 0 and 2.1 v, the device is in the high-impedance state during power up or power down. however, to ensure the high-impedance state above 2.1 v, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the sn54abt162841 is characterized for operation over the full military temperature range of 55 c to 125 c. the sn74abt162841 is characterized for operation from 40 c to 85 c. function table (each 10-bit latch) inputs output oe le d q l h h h l hl l l lx q 0 h x x z
sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 3 post office box 655303 ? dallas, texas 75265 logic symbol 2 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 1q1 2 1q2 3 1q3 5 1q4 6 1q5 8 1d 55 1d1 54 1d2 52 1d3 51 1d4 49 1d5 48 1d6 47 1d7 45 1d8 44 1d9 43 1d10 1q6 9 1q7 10 1q8 12 1q9 13 1q10 14 3d 42 2d1 41 2d2 40 2d3 38 2d4 37 2d5 2q1 15 2q2 16 2q3 17 2q4 19 2q5 20 36 2d6 34 2d7 33 2d8 31 2d9 30 2d10 2q6 21 2q7 23 2q8 24 2q9 26 2q10 27 en2 1 c1 56 1le en4 28 c3 29 2le 1oe 2oe 2 4 logic diagram (positive logic) 1oe to nine other channels 1 56 55 2 1le 1d1 c1 1d 1q1 2oe to nine other channels 28 29 42 15 2le 2d1 c1 1d 2q1
sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high or power-off state, v o 0.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . current into any output in the low state, i o 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) 18 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 2): dgg package 86 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dl package 74 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. the package thermal impedance is calculated in accordance with eia/jedec std jesd51. recommended operating conditions (see note 3) sn54abt162841 sn74abt162841 unit min max min max unit v cc supply voltage 4.5 5.5 4.5 5.5 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 0 v cc 0 v cc v i oh high-level output current 12 12 ma i ol low-level output current 12 12 ma d t/ d v input transition rise or fall rate outputs enabled 10 10 ns/v d t/ d v cc power-up ramp rate 200 200 m s/v t a operating free-air temperature 55 125 40 85 c note 3: unused inputs must be held high or low to prevent them from floating. product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions t a = 25 c sn54abt162841 sn74abt162841 unit parameter test conditions min typ 2 max min max min max unit v ik v cc = 4.5 v, i i = 18 ma 1.2 1.2 1.2 v v cc = 4.5 v, i oh = 1 ma 2.5 2.5 2.5 v oh v cc = 5 v, i oh = 1 ma 3 3 3 v v oh v cc =45v i oh = 3 ma 2.4 2.4 2.4 v v cc = 4 . 5 v i oh = 12 ma 2* 2 v ol v cc =45v i ol = 8 ma 0.4 0.8 0.8 0.65 v v ol v cc = 4 . 5 v i ol = 12 ma 0.55* 0.8 v v hys 100 mv i i v cc = 0 to 5.5 v, v i = v cc or gnd 1 1 1 m a i ozpu 3 v cc = 0 to 2.1 v, v o = 0.5 v to 2.7 v, oe = x 50 50 50 m a i ozpd 3 v cc = 2.1 v to 0, v o = 0.5 v to 2.7 v, oe = x 50 50 50 m a i ozh v cc = 2.1 v to 5.5 v, v o = 2.7 v, oe 2 v 10 10 10 m a i ozl v cc = 2.1 v to 5.5 v, v o = 0.5 v, oe 2 v 10 10 10 m a i off v cc = 0, v i or v o 4.5 v 100 100 m a i cex outputs high v cc = 5.5 v, v o = 5.5 v 50 50 50 m a i o v cc = 5.5 v, v o = 2.5 v 25 75 100 25 100 25 100 ma outputs high v55vi0 0.5 0.5 0.5 i cc outputs low v cc = 5.5 v, i o = 0, v i =v cc or gnd 89 89 89 ma outputs disabled v i = v cc or gnd 0.5 0.5 0.5 d i cc ? v cc = 5.5 v, one input at 3.4 v, other inputs at v cc or gnd 1.5 1.5 1.5 ma c i v i = 2.5 v or 0.5 v 3.5 pf c o v o = 2.5 v or 0.5 v 9 pf * on products compliant to mil-prf-38535, this parameter does not apply. 2 all typical values are at v cc = 5 v. 3 this parameter is characterized, but not production tested. not more than one output should be tested at a time, and the duration of the test should not exceed one second. ? this is the increase in supply current for each input that is at the specified ttl voltage level rather than v cc or gnd. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) v cc = 5 v, t a = 25 c sn54abt162841 sn74abt162841 unit min max min max min max t w pulse duration, le high or low 4 4 4 ns t su setup time, data before le 0.8 0.8 0.8 ns t h hold time, data after le 1.8 1.8 1.8 ns product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice.
sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 6 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 5 v, t a = 25 c sn54abt162841 sn74abt162841 unit (input) (output) min typ max min max min max t plh d q 2.1 3.5 4.5 2.1 5.7 2.1 5.2 ns t phl d q 3 4.3 5.3 3 6.2 3 6 ns t plh le q 2.1 3.5 4.5 2.1 5.6 2.1 5.4 ns t phl le q 2.8 4.1 5.1 2.8 6.1 2.8 5.8 ns t pzh oe q 2 3.6 4.7 2 5.8 2 5.7 ns t pzl oe q 3 4.6 5.7 3 6.7 3 6.5 ns t phz oe q 2.6 4.3 5.7 2.6 6.6 2.6 6.5 ns t plz oe q 2.2 3.6 5.8 2.2 8.4 2.2 7.1 ns
sn54abt162841, sn74abt162841 20-bit bus-interface d-type latches with 3-state outputs scbs665b june 1996 revised may 1997 7 post office box 655303 ? dallas, texas 75265 parameter measurement information 1.5 v t h t su from output under test c l = 50 pf (see note a) load circuit s1 7 v open gnd 500 w 500 w data input timing input 1.5 v 3 v 0 v 1.5 v 1.5 v 3 v 0 v 3 v 0 v 1.5 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 3 v 0 v 1.5 v 1.5 v input 1.5 v output control output waveform 1 s1 at 7 v (see note b) output waveform 2 s1 at open (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v 3.5 v 0 v 1.5 v v ol + 0.3 v 1.5 v v oh 0.3 v 0 v 3 v voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 7 v open test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time with one transition per measurement. 1.5 v figure 1. load circuit and voltage waveforms
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated
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